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sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments scope ? family of testability products members of the texas instruments widebus ? family state-of-the-art 3.3-v abt design supports mixed-mode signal operation (5-v input and output voltages with 3.3-v v cc ) support unregulated battery operation down to 2.7 v ubt ? (universal bus transceiver) combines d-type latches and d-type flip-flops for operation in transparent, latched, or clocked mode bus hold on data inputs eliminates the need for external pullup/pulldown resistors b-port outputs of 'lvth182512 devices have equivalent 25- w series resistors, so no external resistors are required compatible with the ieee std 1149.1-1990 (jtag) test access port and boundary-scan architecture scope ? instruction set ieee std 1149.1-1990 required instructions and optional clamp and highz parallel-signature analysis at inputs pseudo-random pattern generation from outputs sample inputs/toggle outputs binary count from outputs device identification even-parity opcodes package options include 64-pin plastic thin shrink small outline (dgg) and 64-pin ceramic dual flat (hkc) packages using 0.5-mm center-to-center spacings description the 'lvth18512 and 'lvth182512 scan test devices with 18-bit universal bus transceivers are members of the texas instruments scope ? testability integrated-circuit family. this family of devices supports ieee std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. scan access to the test circuitry is accomplished via the 4-wire test access port (tap) interface. additionally, these devices are designed specifically for low-voltage (3.3-v) v cc operation, but with the capability to provide a ttl interface to a 5-v system environment. copyright ? 1997, texas instruments incorporated unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. scope, widebus, and ubt are trademarks of texas instruments incorporated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1clkab 1leab 1oeab 1a1 1a2 gnd 1a3 1a4 1a5 v cc 1a6 1a7 1a8 gnd 1a9 2a1 2a2 2a3 gnd 2a4 2a5 2a6 v cc 2a7 2a8 2a9 gnd 2oeab 2leab 2clkab tdo tms 1clkba 1leba 1oeba 1b1 1b2 gnd 1b3 1b4 1b5 v cc 1b6 1b7 1b8 gnd 1b9 2b1 2b2 2b3 gnd 2b4 2b5 2b6 v cc 2b7 2b8 2b9 gnd 2oeba 2leba 2clkba tdi tck sn54lvth18512, sn54lvth182512 . . . hkc package sn74lvth18512, sn74lvth182512 . . . dgg package (top view)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 2 post office box 655303 ? dallas, texas 75265 description (continued) in the normal mode, these devices are 18-bit universal bus transceivers that combine d-type latches and d-type flip-flops to allow data flow in transparent, latched, or clocked modes. they can be used either as two 9-bit transceivers or one 18-bit transceiver. the test circuitry can be activated by the tap to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. activating the tap in the normal mode does not affect the functional operation of the scope ? universal bus transceivers. data flow in each direction is controlled by output-enable (oeab and oeba ), latch-enable (leab and leba), and clock (clkab and clkba) inputs. for a-to-b data flow, the devices operate in the transparent mode when leab is high. when leab is low, the a data is latched while clkab is held at a static low or high logic level. otherwise, if leab is low, a data is stored on a low-to-high transition of clkab. when oeab is low, the b outputs are active. when oeab is high, the b outputs are in the high-impedance state. b-to-a data flow is similar to a-to-b data flow but uses the oeba , leba, and clkba inputs. in the test mode, the normal operation of the scope ? universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the i/o boundary of the device. when enabled, the test circuitry performs boundary-scan test operations according to the protocol described in ieee std 1149.1-1990. four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (tdi), test data output (tdo), test mode select (tms), and test clock (tck). additionally, the test circuitry performs other testing functions such as parallel-signature analysis (psa) on data inputs and pseudo-random pattern generation (prpg) from data outputs. all testing and scan operations are synchronized to the tap interface. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. the b-port outputs of 'lvth182512, which are designed to source or sink up to 12 ma, include equivalent 25- w series resistors to reduce overshoot and undershoot. the sn54lvth18512 and sn54lvth182512 are characterized for operation over the full military temperature range of 55 c to 125 c. the sn74lvth18512 and sn74lvth182512 are characterized for operation from 40 c to 85 c. function table 2 (normal mode, each register) inputs output oeab leab clkab a b l l l x b 0 3 l l ll l l hh l hxl l l hxhh h x x x z 2 a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkba. 3 output level before the indicated steady-state input conditions were established
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 3 post office box 655303 ? dallas, texas 75265 functional block diagram 2a1 1d c1 1d c1 1d c1 1d c1 boundary-control register bypass register identification register boundary-scan register instruction register tap controller 2leba 2clkba 2oeba tdi tms tck 2b1 tdo 2oeab 2leab 2clkab 1a1 1d c1 1d c1 1d c1 1d c1 1leba 1clkba 1oeba 1b1 1oeab 1leab 1clkab v cc v cc one of nine channels one of nine channels 2 1 3 63 64 62 4 29 30 28 36 35 37 16 34 32 33 61 49 31 v cc v cc v cc v cc
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal name description 1a11a9, 2a12a9 normal-function a-bus i/o ports. see function table for normal-mode logic. 1b11b9, 2b12b9 normal-function b-bus i/o ports. see function table for normal-mode logic. 1clkab, 1clkba, 2clkab, 2clkba normal-function clock inputs. see function table for normal-mode logic. gnd ground 1leab, 1leba, 2leab, 2leba normal-function latch enables. see function table for normal-mode logic. 1oeab , 1oeba , 2oeab , 2oeba normal-function output enables. see function table for normal-mode logic. an internal pullup at each terminal forces the terminal to a high level if left unconnected. tck test clock. one of four terminals required by ieee std 1149.1-1990. test operations of the device are synchronous to tck. data is captured on the rising edge of tck and outputs change on the falling edge of tck. tdi test data input. one of four terminals required by ieee std 1149.1-1990. tdi is the serial input for shifting data through the instruction register or selected data register. an internal pullup forces tdi to a high level if left unconnected. tdo test data output. one of four terminals required by ieee std 1149.1-1990. tdo is the serial output for shifting data through the instruction register or selected data register. tms test mode select. one of four terminals required by ieee std 1149.1-1990. tms directs the device through its tap controller states. an internal pullup forces tms to a high level if left unconnected. v cc supply voltage
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 5 post office box 655303 ? dallas, texas 75265 test architecture serial-test information is conveyed by means of a 4-wire test bus or tap, that conforms to ieee std 1149.1-1990. test instructions, test data, and test control signals all are passed along this serial-test bus. the tap controller monitors two signals from the test bus, tck and tms. the tap controller extracts the synchronization (tck) and state control (tms) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. figure 1 shows the tap-controller state diagram. the tap controller is fully synchronous to the tck signal. input data is captured on the rising edge of tck and output data changes on the falling edge of tck. this scheme ensures data to be captured is valid for fully one-half of the tck cycle. the functional block diagram shows the ieee std 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the tap controller, and the test registers. as shown, the device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register. test-logic-reset run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr update-dr tms = l tms = l tms = h tms = l tms = h tms = h tms = l tms = h tms = l tms = l tms = h tms = l exit2-dr select-ir-scan capture-ir shift-ir exit1-ir pause-ir update-ir tms = l tms = l tms = h tms = l tms = h tms = h tms = l tms = h tms = l exit2-ir tms = l tms = h tms = h tms = h tms = l tms = h tms = l tms = h tms = h tms = h tms = l figure 1. tap-controller state diagram
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 6 post office box 655303 ? dallas, texas 75265 state diagram description the tap controller is a synchronous finite-state machine that provides test control signals throughout the device. the state diagram shown in figure 1 is in accordance with ieee std 1149.1-1990. the tap controller proceeds through its states based on the level of tms at the rising edge of tck. as shown, the tap controller consists of 16 states. there are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. a stable state is a state the tap controller can retain for consecutive tck cycles. any state that does not meet this criterion is an unstable state. there are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. only one register can be accessed at a time. test-logic-reset the device powers up in the test-logic-reset state. in the stable test-logic-reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. the instruction register is reset to an opcode that selects the optional idcode instruction, if supported, or the bypass instruction. certain data registers can also be reset to their power-up values. the state machine is constructed such that the tap controller returns to the test-logic-reset state in no more than five tck cycles if tms is left high. the tms pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. for the 'lvth18512 and 'lvth182512, the instruction register is reset to the binary value 10000001, which selects the idcode instruction. bits 4744 in the boundary-scan register are reset to logic 1, ensuring that these cells, which control a-port and b-port outputs, are set to benign values (i.e., if test mode were invoked the outputs would be at the high-impedance state). reset-value of other bits in the boundary-scan register should be considered indeterminate. the boundary-control register is reset to the binary value 010, which selects the psa test operation. run-test/idle the tap controller must pass through the run-test /idle state (from test-logic-reset) before executing any test operations. the run-test /idle state also can be entered following data-register or instruction-register scans. run-test/idle is a stable state in which the test logic can be actively running a test or can be idle. the test operations selected by the boundary-control register are performed while the tap controller is in the run-test /idle state. select-dr-scan, select-lr-scan no specific function is performed in the select-dr-scan and select-lr-scan states, and the tap controller exits either of these states on the next tck cycle. these states allow the selection of either data-register scan or instruction-register scan. capture-dr when a data-register scan is selected, the tap controller must pass through the capture-dr state. in the capture-dr state, the selected data register captures a data value as specified by the current instruction. such capture operations occur on the rising edge of tck, upon which the tap controller exits the capture-dr state.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 7 post office box 655303 ? dallas, texas 75265 shift-dr upon entry to the shift-dr state, the data register is placed in the scan path between tdi and tdo, and on the first falling edge of tck, tdo goes from the high-impedance state to an active state. tdo enables to the logic level present in the least-significant bit of the selected data register. while in the stable shift-dr state, data is serially shifted through the selected data register on each tck cycle. the first shift occurs on the first rising edge of tck after entry to the shift-dr state (i.e., no shifting occurs during the tck cycle in which the tap controller changes from capture-dr to shift-dr or from exit2-dr to shift-dr). the last shift occurs on the rising edge of tck, upon which the tap controller exits the shift-dr state. exit1-dr, exit2-dr the exit1-dr and exit2-dr states are temporary states that end a data-register scan. it is possible to return to the shift-dr state from either exit1-dr or exit2-dr without recapturing the data register. on the first falling edge of tck after entry to exit1-dr, tdo goes from the active state to the high-impedance state. pause-dr no specific function is performed in the stable pause-dr state, in which the tap controller can remain indefinitely. the pause-dr state suspends and resumes data-register scan operations without loss of data. update-dr if the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of tck, following entry to the update-dr state. capture-ir when an instruction-register scan is selected, the tap controller must pass through the capture-ir state. in the capture-ir state, the instruction register captures its current status value. this capture operation occurs on the rising edge of tck, upon which the tap controller exits the capture-ir state. for the 'lvth18512 and 'lvth182512, the status value loaded in the capture-ir state is the fixed binary value 10000001. shift-ir upon entry to the shift-ir state, the instruction register is placed in the scan path between tdi and tdo. on the first falling edge of tck, tdo goes from the high-impedance state to the active state. tdo enables to the logic level present in the least-significant bit of the instruction register. while in the stable shift-ir state, instruction data is serially shifted through the instruction register on each tck cycle. the first shift occurs on the first rising edge of tck after entry to the shift-ir state (i.e., no shifting occurs during the tck cycle in which the tap controller changes from capture-ir to shift-ir or from exit2-ir to shift-ir). the last shift occurs on the rising edge of tck, upon which the tap controller exits the shift-ir state. exit1-ir, exit2-ir the exit1-ir and exit2-ir states are temporary states that end an instruction-register scan. it is possible to return to the shift-ir state from either exit1-ir or exit2-ir without recapturing the instruction register. on the first falling edge of tck after entry to exit1-ir, tdo goes from the active state to the high-impedance state. pause-ir no specific function is performed in the stable pause-ir state, in which the tap controller can remain indefinitely. the pause-ir state suspends and resumes instruction-register scan operations without loss of data. update-ir the current instruction is updated and takes effect on the falling edge of tck, following entry to the update-ir state.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 8 post office box 655303 ? dallas, texas 75265 register overview with the exception of the bypass and device-identification registers, any test register can be thought of as a serial shift register with a shadow latch on each bit. the bypass and device-identification registers differ in that they contain only a shift register. during the appropriate capture state (capture-ir for instruction register, capture-dr for data registers), the shift register can be parallel loaded from a source specified by the current instruction. during the appropriate shift state (shift-ir or shift-dr), the contents of the shift register are shifted out from tdo while new contents are shifted in at tdi. during the appropriate update state (update-ir or update-dr), the shadow latches are updated from the shift register. instruction register description the instruction register (ir) is eight bits long and tells the device what instruction is to be executed. information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during capture-dr. table 3 lists the instructions supported by the 'lvth18512 and 'lvth182512. the even-parity feature specified for scope ? devices is supported in this device. bit 7 of the instruction opcode is the parity bit. any instructions that are defined for scope ? devices but are not supported by this device default to bypass. during capture-ir, the ir captures the binary value 10000001. as an instruction is shifted in, this value is shifted out via tdo and can be inspected as verification that the ir is in the scan path. during update-ir, the value that has been shifted into the ir is loaded into shadow latches. at this time, the current instruction is updated and any specified mode change takes effect. at power up or in the test-logic-reset state, the ir is reset to the binary value 10000001, which selects the idcode instruction. the ir order of scan is shown in figure 2. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 tdo tdi bit 7 parity (msb) bit 0 (lsb) figure 2. instruction register order of scan
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 9 post office box 655303 ? dallas, texas 75265 data register description boundary-scan register the boundary-scan register (bsr) is 48 bits long. it contains one boundary-scan cell (bsc) for each normal-function input pin and one bsc for each normal-function i/o pin (one single cell for both input data and output data). the bsr is used to store test data that is to be applied externally to the device output pins, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. the source of data to be captured into the bsr during capture-dr is determined by the current instruction. the contents of the bsr can change during run-test /idle as determined by the current instruction. at power up or in test-logic-reset, bscs 4744 are reset to logic 1, ensuring that these cells, which control a-port and b-port outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at the high-impedance state). reset values of other bscs should be considered indeterminate. the bsr order of scan is from tdi through bits 470 to tdo. table 1 shows the bsr bits and their associated device pin signals. table 1. boundary-scan register configuration bsr bit number device signal bsr bit number device signal bsr bit number device signal 47 2oeab 35 2a9-i/o 17 2b9-i/o 46 1oeab 34 2a8-i/o 16 2b8-i/o 45 2oeba 33 2a7-i/o 15 2b7-i/o 44 1oeba 32 2a6-i/o 14 2b6-i/o 43 2clkab 31 2a5-i/o 13 2b5-i/o 42 1clkab 30 2a4-i/o 12 2b4-i/o 41 2clkba 29 2a3-i/o 11 2b3-i/o 40 1clkba 28 2a2-i/o 10 2b2-i/o 39 2leab 27 2a1-i/o 9 2b1-i/o 38 1leab 26 1a9-i/o 8 1b9-i/o 37 2leba 25 1a8-i/o 7 1b8-i/o 36 1leba 24 1a7-i/o 6 1b7-i/o 23 1a6-i/o 5 1b6-i/o 22 1a5-i/o 4 1b5-i/o 21 1a4-i/o 3 1b4-i/o 20 1a3-i/o 2 1b3-i/o 19 1a2-i/o 1 1b2-i/o 18 1a1-i/o 0 1b1-i/o
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 10 post office box 655303 ? dallas, texas 75265 boundary-control register the boundary-control register (bcr) is three bits long. the bcr is used in the context of the boundary-run test (runt) instruction to implement additional test operations not included in the basic scope ? instruction set. such operations include prpg, psa, and binary count up (count). table 4 shows the test operations that are decoded by the bcr. during capture-dr, the contents of the bcr are not changed. at power up or in test-logic-reset, the bcr is reset to the binary value 010, which selects the psa test operation. the bcr order of scan is shown in figure 3. bit 0 (lsb) tdo tdi bit 1 bit 2 (msb) figure 3. boundary-control register order of scan bypass register the bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, reducing the number of bits per test pattern that must be applied to complete a test operation. during capture-dr, the bypass register captures a logic 0. the bypass register order of scan is shown in figure 4. bit 0 tdo tdi figure 4. bypass register order of scan
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 11 post office box 655303 ? dallas, texas 75265 device-identification register the device-identification register (idr) is 32 bits long. it can be selected and read to identify the manufacturer, part number, and version of this device. for the 'lvth18512, the binary value 00000000000000111011000000101111 (0003b02f, hex) is captured (during capture-dr state) in the idr to identify this device as texas instruments sn54/74lvth18512. for the 'lvth182512, the binary value 00000000000000111100000000101111 (0003c02f, hex) is captured (during capture-dr state) in the device-identification register to identify this device as texas instruments sn54/74lvth182512. the idr order of scan is from tdi through bits 310 to tdo. table 2 shows the idr bits and their significance. table 2. device-identification register configuration idr bit number identification significance idr bit number identification significance idr bit number identification significance 31 version3 27 partnumber15 11 manufacturer10 2 30 version2 26 partnumber14 10 manufacturer09 2 29 version1 25 partnumber13 9 manufacturer08 2 28 version0 24 partnumber12 8 manufacturer07 2 23 partnumber11 7 manufacturer06 2 22 partnumber10 6 manufacturer05 2 21 partnumber09 5 manufacturer04 2 20 partnumber08 4 manufacturer03 2 19 partnumber07 3 manufacturer02 2 18 partnumber06 2 manufacturer01 2 17 partnumber05 1 manufacturer00 2 16 partnumber04 0 logic1 2 15 partnumber03 14 partnumber02 13 partnumber01 12 partnumber00 2 note that for ti products, bits 110 of the device-identification register always contain the binary value 000000101111 (02f, hex).
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 12 post office box 655303 ? dallas, texas 75265 instruction-register opcode description the instruction-register opcodes are shown in table 3. the following descriptions detail the operation of each instruction. table 3. instruction-register opcodes binary code 2 bit 7 bit 0 msb lsb scope opcode description selected data register mode 00000000 extest boundary scan boundary scan test 10000001 idcode identification read device identification normal 10000010 sample/preload sample boundary boundary scan normal 00000011 bypass 3 bypass scan bypass normal 10000100 bypass 3 bypass scan bypass normal 00000101 bypass 3 bypass scan bypass normal 00000110 highz control boundary to high impedance bypass modified test 10000111 clamp control boundary to 1/0 bypass test 10001000 bypass 3 bypass scan bypass normal 00001001 runt boundary-run test bypass test 00001010 readbn boundary read boundary scan normal 10001011 readbt boundary read boundary scan test 00001100 celltst boundary self test boundary scan normal 10001101 tophip boundary toggle outputs bypass test 10001110 scancn boundary-control register scan boundary control normal 00001111 scanct boundary-control register scan boundary control test all others bypass bypass scan bypass normal 2 bit 7 is used to maintain even parity in the 8-bit instruction. 3 the bypass instruction is executed in lieu of a scope ? instruction that is not supported in the 'lvth18512 or 'lvth182512. boundary scan this instruction conforms to the ieee std 1149.1-1990 extest instruction. the bsr is selected in the scan path. data appearing at the device input and i/o pins is captured in the associated bscs. data that has been scanned into the i/o bscs for pins in the output mode is applied to the device i/o pins. data present at the device pins, except for output enables, is passed through the bscs to the normal on-chip logic. for i/o pins, the operation of a pin as input or output is determined by the contents of the output-enable bscs (bits 4744 of the bsr). when a given output enable is active (logic 0), the associated i/o pins operate in the output mode. otherwise, the i/o pins operate in the input mode. the device operates in the test mode. identification read this instruction conforms to the ieee std 1149.1-1990 idcode instruction. the idr is selected in the scan path. the device operates in the normal mode. sample boundary this instruction conforms to the ieee std 1149.1-1990 sample/preload instruction. the bsr is selected in the scan path. data appearing at the device input pins and i/o pins in the input mode is captured in the associated bscs, while data appearing at the outputs of the normal on-chip logic is captured in the bscs associated with i/o pins in the output mode. the device operates in the normal mode.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 13 post office box 655303 ? dallas, texas 75265 bypass scan this instruction conforms to the ieee std 1149.1-1990 bypass instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in the normal mode. control boundary to high impedance this instruction conforms to the ieee std 1149.1a-1993 highz instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in a modified test mode in which all device i/o pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 this instruction conforms to the ieee std 1149.1a-1993 clamp instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. data in the i/o bscs for pins in the output mode is applied to the device i/o pins. the device operates in the test mode. boundary-run test the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in the test mode. the test operation specified in the bcr is executed during run-test /idle. the five test operations decoded by the bcr are: sample inputs/toggle outputs (topsip), prpg, psa, simultaneous psa and prpg (psa/prpg), and simultaneous psa and binary count up (psa/count). boundary read the bsr is selected in the scan path. the value in the bsr remains unchanged during capture-dr. this instruction is useful for inspecting data after a psa operation. boundary self test the bsr is selected in the scan path. all bscs capture the inverse of their current values during capture-dr. in this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the bsr. the device operates in the normal mode. boundary toggle outputs the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. data in the shift-register elements of the selected output-mode bscs is toggled on each rising edge of tck in run-test /idle and is then updated in the shadow latches and thereby applied to the associated device i/o pins on each falling edge of tck in run-test /idle. data in the input-mode bscs remains constant. data appearing at the device input or i/o pins is not captured in the input-mode bscs. the device operates in the test mode. boundary-control-register scan the bcr is selected in the scan path. the value in the bcr remains unchanged during capture-dr. this operation must be performed before a boundary-run test operation to specify which test operation is to be executed.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 14 post office box 655303 ? dallas, texas 75265 boundary-control-register opcode description the bcr opcodes are decoded from bcr bits 20 as shown in table 4. the selected test operation is performed while the runt instruction is executed in the run-test /idle state. the following descriptions detail the operation of each bcr instruction and illustrate the associated psa and prpg algorithms. table 4. boundary-control register opcodes binary code bit 2 bit 0 msb lsb description x00 sample inputs/toggle outputs (topsip) x01 pseudo-random pattern generation/36-bit mode (prpg) x10 parallel-signature analysis/36-bit mode (psa) 011 simultaneous psa and prpg/18-bit mode (psa/prpg) 111 simultaneous psa and binary count up/18-bit mode (psa/count) while the control input bscs (bits 4736) are not included in the toggle, psa, prpg, or count algorithms, the output-enable bscs (bits 4744 of the bsr) control the drive state (active or high impedance) of the selected device output pins. these bcr instructions are only valid when both bytes of the device are operating in one direction of data flow (i.e., 1oeab 1oeba and 2oeab 2oeba ) and in the same direction of data flow (i.e., 1oeab = 2oeab and 1oeba = 2oeba ). otherwise, the bypass instruction is operated. sample inputs/toggle outputs (topsip) data appearing at the selected device input-mode i/o pins is captured in the shift-register elements of the associated bscs on each rising edge of tck. data in the shift-register elements of the selected output-mode bscs is toggled on each rising edge of tck, updated in the shadow latches, and applied to the associated device i/o pins on each falling edge of tck.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 15 post office box 655303 ? dallas, texas 75265 pseudo-random pattern generation (prpg) a pseudo-random pattern is generated in the shift-register elements of the selected bscs on each rising edge of tck, updated in the shadow latches, and applied to the associated device output-mode i/o pins on each falling edge of tck. figures 5 and 6 show the 36-bit linear-feedback shift-register algorithms through which the patterns are generated. an initial seed value should be scanned into the bsr before performing this operation. a seed value of all zeroes does not produce additional patterns. = 1b8-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b9-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a8-i/o 1a9-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a8-i/o 2a9-i/o 2b8-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b9-i/o figure 5. 36-bit prpg configuration (1oeab = 2oeab = 0, 1oeba = 2oeba = 1)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 16 post office box 655303 ? dallas, texas 75265 1a8-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a9-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b8-i/o 1b9-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b8-i/o 2b9-i/o 2a8-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a9-i/o = figure 6. 36-bit prpg configuration (1oeab = 2oeab = 1, 1oeba = 2oeba = 0)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 17 post office box 655303 ? dallas, texas 75265 parallel-signature analysis (psa) data appearing at the selected device input-mode i/o pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected bscs on each rising edge of tck. data in the shadow latches of the selected output-mode bscs remains constant and is applied to the associated device i/o pins. figures 7 and 8 show the 36-bit linear-feedback shift-register algorithms through which the signature is generated. an initial seed value should be scanned into the bsr before performing this operation. = 1b8-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b9-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a8-i/o 1a9-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a8-i/o 2a9-i/o 2b8-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b9-i/o = figure 7. 36-bit psa configuration (1oeab = 2oeab = 0, 1oeba = 2oeba = 1)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 18 post office box 655303 ? dallas, texas 75265 1a8-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a9-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b8-i/o 1b9-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b8-i/o 2b9-i/o 2a8-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a9-i/o = = figure 8. 36-bit psa configuration (1oeab = 2oeab = 1, 1oeba = 2oeba = 0)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 19 post office box 655303 ? dallas, texas 75265 simultaneous psa and prpg (psa/prpg) data appearing at the selected device input-mode i/o pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode bscs on each rising edge of tck. at the same time, an 18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode bscs on each rising edge of tck, updated in the shadow latches, and applied to the associated device i/o pins on each falling edge of tck. figures 9 and 10 show the 18-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. an initial seed value should be scanned into the bsr before performing this operation. a seed value of all zeroes does not produce additional patterns. 1b8-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b9-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a8-i/o 1a9-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a8-i/o 2a9-i/o 2b8-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b9-i/o = = figure 9. 18-bit psa/prpg configuration (1oeab = 2oeab = 0, 1oeba = 2oeba = 1)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 20 post office box 655303 ? dallas, texas 75265 1a8-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a9-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b8-i/o 1b9-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b8-i/o 2b9-i/o 2a8-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a9-i/o = = figure 10. 18-bit psa/prpg configuration (1oeab = 2oeab = 1, 1oeba = 2oeba = 0)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 21 post office box 655303 ? dallas, texas 75265 simultaneous psa and binary count up (psa/count) data appearing at the selected device input-mode i/o pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode bscs on each rising edge of tck. at the same time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode bscs on each rising edge of tck, updated in the shadow latches, and applied to the associated device i/o pins on each falling edge of tck. figures 11 and 12 show the 18-bit linear-feedback shift-register algorithms through which the signature is generated. an initial seed value should be scanned into the bsr before performing this operation. 1b8-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b9-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a8-i/o 1a9-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a8-i/o 2a9-i/o 2b8-i/o 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b9-i/o msb lsb = = figure 11. 18-bit psa/count configuration (1oeab = 2oeab = 0, 1oeba = 2oeba = 1)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 22 post office box 655303 ? dallas, texas 75265 1a8-i/o 1a7-i/o 1a6-i/o 1a5-i/o 1a4-i/o 1a3-i/o 1a2-i/o 1a1-i/o 1a9-i/o 1b7-i/o 1b6-i/o 1b5-i/o 1b4-i/o 1b3-i/o 1b2-i/o 1b1-i/o 1b8-i/o msb 2b7-i/o 2b6-i/o 2b5-i/o 2b4-i/o 2b3-i/o 2b2-i/o 2b1-i/o 2b8-i/o 2b9-i/o 2a8-i/o 2a7-i/o 2a6-i/o 2a5-i/o 2a4-i/o 2a3-i/o 2a2-i/o 2a1-i/o 2a9-i/o lsb 1b9-i/o = = figure 12. 18-bit psa/count configuration (1oeab = 2oeab = 1, 1oeba = 2oeba = 0)
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 23 post office box 655303 ? dallas, texas 75265 timing description all test operations of the 'lvth18512 and 'lvth182512 are synchronous to the tck signal. data on the tdi, tms, and normal-function inputs is captured on the rising edge of tck. data appears on the tdo and normal-function output pins on the falling edge of tck. the tap controller is advanced through its states (as shown in figure 1) by changing the value of tms on the falling edge of tck and then applying a rising edge to tck. a simple timing example is shown in figure 13. in this example, the tap controller begins in the test-logic-reset state and is advanced through its states, as necessary, to perform one instruction-register scan and one data-register scan. while in the shift-ir and shift-dr states, tdi is used to input serial data, and tdo is used to output serial data. the tap controller is then returned to the test-logic-reset state. table 5 details the operation of the test circuitry during each tck cycle. table 5. explanation of timing example tck cycle(s) tap state after tck description 1 test-logic-reset tms is changed to a logic 0 value on the falling edge of tck to begin advancing the tap controller toward the desired state. 2 run-test/idle 3 select-dr-scan 4 select-ir-scan 5 capture-ir the ir captures the 8-bit binary value 10000001 on the rising edge of tck as the tap controller exits the capture-ir state. 6 shift-ir tdo becomes active and tdi is made valid on the falling edge of tck. the first bit is shifted into the tap on the rising edge of tck as the tap controller advances to the next state. 713 shift-ir one bit is shifted into the ir on each tck rising edge. with tdi held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the ir. at the same time, the 8-bit binary value 10000001 is serially scanned out of the ir via tdo. in tck cycle 13, tms is changed to a logic 1 value to end the ir scan on the next tck cycle. the last bit of the instruction is shifted as the tap controller advances from shift-ir to exit1-ir. 14 exit1-ir tdo becomes inactive (goes to the high-impedance state) on the falling edge of tck. 15 update-ir the ir is updated with the new instruction (bypass) on the falling edge of tck. 16 select-dr-scan 17 capture-dr the bypass register captures a logic 0 value on the rising edge of tck as the tap controller exits the capture-dr state. 18 shift-dr tdo becomes active and tdi is made valid on the falling edge of tck. the first bit is shifted into the tap on the rising edge of tck as the tap controller advances to the next state. 1920 shift-dr the binary value 101 is shifted in via tdi, while the binary value 010 is shifted out via tdo. 21 exit1-dr tdo becomes inactive (goes to the high-impedance state) on the falling edge of tck. 22 update-dr the selected data register is updated with the new data on the falling edge of tck. 23 select-dr-scan 24 select-ir-scan 25 test-logic-reset test operation completed
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 24 post office box 655303 ? dallas, texas 75265 ?????? ?????? ?????? ?????? ????????? ????????? ????????? ????????? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ?????? ?????? ?????? ?????? test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir update-ir select-dr-scan capture-dr shift-dr exit1-dr update-dr select-dr-scan select-ir-scan test-logic-reset tck tms tdi tdo ?? ?? tap controller state 3-state (tdo) or don't care (tdi) figure 13. timing example absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or power-off state, v o (see note 1) 0.5 v to 7 v . . . . . . . . . current into any output in the low state, i o : sn54lvth18512 96 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn54lvth182512 (a port or tdo) 96 ma . . . . . . . . . . . . . . . . . . sn54lvth182512 (b port) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . sn74lvth18512 128 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn74lvth182512 (a port or tdo) 128 ma . . . . . . . . . . . . . . . . . sn74lvth182512 (b port) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . current into any output in the high state, i o (see note 2): sn54lvth18512 48 ma . . . . . . . . . . . . . . . . . . . . . sn54lvth182512 (a port or tdo) 48 ma . . . . . . sn54lvth182512 (b port) 30 ma . . . . . . . . . . . . . sn74lvth18512 64 ma . . . . . . . . . . . . . . . . . . . . . sn74lvth182512 (a port or tdo) 64 ma . . . . . . sn74lvth182512 (b port) 30 ma . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 3): dgg package 73 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observe d. 2. this current only flows when the output is in the high state and v o > v cc . 3. the package thermal impedance is calculated in accordance with jesd 51.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 25 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 4) sn54lvth18512 sn74lvth18512 unit min max min max unit v cc supply voltage 2.7 3.6 2.7 3.6 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 5.5 5.5 v i oh high-level output current 24 32 ma i ol low-level output current 24 32 ma i ol 2 low-level output current 48 64 ma d t/ d v input transition rise or fall rate outputs enabled 10 10 ns/v t a operating free-air temperature 55 125 40 85 c 2 current duty cycle 50%, f 1 khz note 4: unused control inputs must be held high or low to prevent them from floating. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 26 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions sn54lvth18512 sn74lvth18512 unit parameter test conditions min typ 2 max min typ 2 max unit v ik v cc = 2.7 v, i i = 18 ma 1.2 1.2 v v cc = 2.7 v to 3.6 v, i oh = 100 m a v cc 0.2 v cc 0.2 v cc = 2.7 v, i oh = 3 ma 2.4 2.4 v oh i oh = 8 ma 2.4 2.4 v v cc = 3 v i oh = 24 ma 2 i oh = 32 ma 2 v cc =27v i ol = 100 m a 0.2 0.2 v cc = 2 . 7 v i ol = 24 ma 0.5 0.5 v ol i ol = 16 ma 0.4 0.4 v v ol v cc =3v i ol = 32 ma 0.5 0.5 v v cc = 3 v i ol = 48 ma 0.55 i ol = 64 ma 0.55 clk , v cc = 3.6 v, v i = v cc or gnd 1 1 clk, le, tck v cc = 0 or 3.6 v, v i = 5.5 v 10 10 oe v i = 5.5 v 5 5 i i oe, tdi tms v cc = 3.6 v v i = v cc 1 1 m a i i tdi , tms v i = 0 25 100 25 100 m a ab v i = 5.5 v 20 20 a or b p orts 3 v cc = 3.6 v v i = v cc 1 1 orts 3 v i = 0 5 5 i off v cc = 0, v i or v o = 0 to 4.5 v 100 m a i a or b v cc =3v v i = 0.8 v 75 500 75 150 500 m a i i(hold) ports v cc = 3 v v i = 2 v 75 500 75 150 500 m a i ozh tdo v cc = 3.6 v, v o = 3 v 1 1 m a i ozl tdo v cc = 3.6 v, v o = 0.5 v 1 1 m a i ozpu tdo v cc = 0 to 1.5 v, v o = 0.5 v or 3 v 50 50 m a i ozpd tdo v cc = 1.5 v to 0, v o = 0.5 v or 3 v 50 50 m a v cc = 3.6 v, outputs high 0.6 2 0.6 2 i cc v cc = 3 . 6 v , i o = 0, outputs low 18 24 18 24 ma v i = v cc or gnd outputs disabled 0.6 2 0.6 2 d i cc ? v cc = 3 v to 3.6 v, one input at v cc 0.6 v, other inputs at v cc or gnd 0.5 0.5 ma c i v i = 3 v or 0 4 4 pf c io v o = 3 v or 0 10 10 pf c o v o = 3 v or 0 8 8 pf 2 all typical values are at v cc = 3.3 v, t a = 25 c. 3 unused pins at v cc or gnd the parameter i i(hold) includes the off-state output leakage current. ? this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 27 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see figure 14) sn54lvth18512 sn74lvth18512 v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f clock clock frequency clkab or clkba 0 100 0 80 0 100 0 80 mhz t pulse duration clkab or clkba high or low 4.4 5.6 4.4 5.6 ns t w p u lse d u ration leab or leba high 3 3 3 3 ns t st ti a before clkab or b before clkba 2.8 3 2.8 3 t su setup time a before leab or clk high 1.5 0.7 1.5 0.7 ns a before leab ?? ? ????? ???? clk low 1.6 1.6 1.6 1.6 t h hold time a after clkab or b after clkba 1.4 1.1 1.4 1.1 ns h a after leab or b after leba 3.1 3.5 3.1 3.5 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see figure 14) sn54lvth18512 sn74lvth18512 v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f clock clock frequency tck 0 50 0 40 0 50 0 40 mhz t w pulse duration tck high or low 9.5 10.5 9.5 10.5 ns t st ti a, b, clk, le, or oe before tck 6.5 7 6.5 7 t su setup time tdi before tck 2.5 3.5 2.5 3.5 ns tms before tck 2.5 3.5 2.5 3.5 a, b, clk, le, or oe after tck 1.7 1 1.7 1 t h hold time tdi after tck 1.5 1 1.5 1 ns tms after tck 1.5 1 1.5 1 t d delay time power up to tck 50 50 50 50 ns t r rise time v cc power up 1 1 1 1 m s product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 28 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see figure 14) sn54lvth18512 sn74lvth18512 parameter from (input) to (output) v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f max clkab or clkba 100 80 100 80 mhz t plh aorb bora 1.5 5.1 5.8 1.5 4.9 5.6 ns t phl a or b b or a 1.5 5.1 5.8 1.5 4.9 5.6 ns t plh clkab or clkba bora 1.5 6.3 7.2 1.5 5.8 6.8 ns t phl clkab or clkba b or a 1.5 6.3 7.2 1.5 5.8 6.8 ns t plh leab or leba bora 1.5 7.8 9.2 1.5 7.4 8.4 ns t phl leab or leba b or a 1.5 6 6.6 1.5 5.7 6.4 ns t pzh oeab or oeba bora 1.5 7.6 8.5 1.5 7.1 8.3 ns t pzl oeab or oeba b or a 1.5 7.6 8.5 1.5 7.1 8.3 ns t phz oeab or oeba bora 2.5 8.3 8.8 2.5 7.8 8.4 ns t plz oeab or oeba b or a 2.5 8.3 8.8 2.5 7.8 8.4 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see figure 14) sn54lvth18512 sn74lvth18512 parameter from (input) to (output) v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f max tck 50 40 50 40 mhz t plh tck ???? ?? ? ? ?? ? ?? ?? ? ?? ??k ? ?? ? ?? ? ? ?? ? ?? ?? ? ?? ??k ?? ? M ? ? ? M? ?? ? ?? ??k ?? ?? ? ?? M? ?? ?? ? ?? ??k ???? ? ?? ?? ? ?? ? ?? ??k ? ?? ? ? ?? ?? ? ?? ? ?? ??k ?? ? M ? ? ? M? ?? ? ?? ??k ?? ?? M ? ?? ? M? ?? ? ?? ??k ???? ? ?? ? ? ?? ? ?? ??k ? ?? ? ? ??? ?? ??? ?? ? ?? ??k ?? ?? ?? ?? ? ?? ?? ? ?? ??k ?? ?? ?? ?? ?? ? ?? product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 29 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 4) sn54lvth182512 sn74lvth182512 unit min max min max unit v cc supply voltage 2.7 3.6 2.7 3.6 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 5.5 5.5 v i oh high level out p ut current a port, tdo 24 32 ma i oh high - le v el o u tp u t c u rrent b port 12 12 ma i ol low level out p ut current a port, tdo 24 32 ma i ol lo w- le v el o u tp u t c u rrent b port 12 12 ma i ol 2 low-level output current a port, tdo 48 64 ma d t/ d v input transition rise or fall rate outputs enabled 10 10 ns/v t a operating free-air temperature 55 125 40 85 c 2 current duty cycle 50%, f 1 khz note 4: unused control inputs must be held high or low to prevent them from floating. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 30 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions sn54lvth182512 sn74lvth182512 unit parameter test conditions min typ 2 max min typ 2 max unit v ik v cc = 2.7 v, i i = 18 ma 1.2 1.2 v a, b, tdo v cc = 2.7 v to 3.6 v, i oh = 100 m a v cc 0.2 v cc 0.2 v cc = 2.7 v, i oh = 3 ma 2.4 2.4 v oh a port, i oh = 8 ma 2.4 2.4 v v oh , tdo v cc = 3 v i oh = 24 ma 2 v i oh = 32 ma 2 b port v cc = 3 v, i oh = 12 ma 2 2 a, b, tdo v cc = 2.7 v, i ol = 100 m a 0.2 0.2 v cc = 2.7 v, i ol = 24 ma 0.5 0.5 at i ol = 16 ma 0.4 0.4 v ol a port, tdo v cc =3v i ol = 32 ma 0.5 0.5 v tdo v cc = 3 v i ol = 48 ma 0.55 i ol = 64 ma 0.55 b port v cc = 3 v, i ol = 12 ma 0.8 0.8 clk , v cc = 3.6 v, v i = v cc or gnd 1 1 clk, le, tck v cc = 0 or 3.6 v, v i = 5.5 v 10 10 oe v i = 5.5 v 5 5 i i oe, tdi tms v cc = 3.6 v v i = v cc 1 1 m a i i tdi , tms v i = 0 25 100 25 100 m a ab v i = 5.5 v 20 20 a or b p orts 3 v cc = 3.6 v v i = v cc 1 1 orts 3 v i = 0 5 5 i off v cc = 0, v i or v o = 0 to 4.5 v 100 m a i a or b v cc =3v v i = 0.8 v 75 500 75 150 500 m a i i(hold) ports v cc = 3 v v i = 2 v 75 500 75 150 500 m a i ozh tdo v cc = 3.6 v, v o = 3 v 1 1 m a i ozl tdo v cc = 3.6 v, v o = 0.5 v 1 1 m a i ozpu tdo v cc = 0 to 1.5 v, v o = 0.5 v or 3 v 50 50 m a i ozpd tdo v cc = 1.5 v to 0, v o = 0.5 v or 3 v 50 50 m a v cc = 3.6 v, outputs high 0.6 2 0.6 2 i cc v cc = 3 . 6 v , i o = 0, outputs low 18 24 18 24 ma v i = v cc or gnd outputs disabled 0.6 2 0.6 2 d i cc ? v cc = 3 v to 3.6 v, one input at v cc 0.6 v, other inputs at v cc or gnd 0.5 0.5 ma c i v i = 3 v or 0 4 4 pf c io v o = 3 v or 0 10 10 pf c o v o = 3 v or 0 8 8 pf 2 all typical values are at v cc = 3.3 v, t a = 25 c. 3 unused pins at v cc or gnd the parameter i i(hold) includes the off-state output leakage current. ? this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 31 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see figure 14) sn54lvth182512 sn74lvth182512 v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f clock clock frequency clkab or clkba 0 100 0 80 0 100 0 80 mhz t pulse duration clkab or clkba high or low 4.4 5.6 4.4 5.6 ns t w p u lse d u ration leab or leba high 3 3 3 3 ns t st ti a before clkab or b before clkba 2.8 3 2.8 3 t su setup time a before leab or clk high 1.5 0.7 1.5 0.7 ns a before leab ?? ? ????? ???? clk low 1.6 1.6 1.6 1.6 t h hold time a after clkab or b after clkba 1.4 1.1 1.4 1.1 ns h a after leab or b after leba 3.1 3.5 3.1 3.5 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see figure 14) sn54lvth182512 sn74lvth182512 v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f clock clock frequency tck 0 50 0 40 0 50 0 40 mhz t w pulse duration tck high or low 9.5 10.5 9.5 10.5 ns t st ti a, b, clk, le, or oe before tck 6.5 7 6.5 7 t su setup time tdi before tck 2.5 3.5 2.5 3.5 ns tms before tck 2.5 3.5 2.5 3.5 a, b, clk, le, or oe after tck 1.7 1 1.7 1 t h hold time tdi after tck 1.5 1 1.5 1 ns tms after tck 1.5 1 1.5 1 t d delay time power up to tck 50 50 50 50 ns t r rise time v cc power up 1 1 1 1 m s product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 32 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see figure 14) sn54lvth182512 sn74lvth182512 parameter from (input) to (output) v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f max clkab or clkba 100 80 100 80 mhz t plh a b 1.5 6 6.7 1.5 5.7 6.4 ns t phl a b 1.5 6 6.7 1.5 5.7 6.4 ns t plh b a 1.5 5.1 5.8 1.5 4.9 5.6 ns t phl b a 1.5 5.1 5.8 1.5 4.9 5.6 ns t plh clkab b 1.5 7.1 8.1 1.5 6.7 7.7 ns t phl clkab b 1.5 7.1 8.1 1.5 6.7 7.7 ns t plh clkba a 1.5 6.3 7.2 1.5 5.8 6.8 ns t phl clkba a 1.5 6.3 7.2 1.5 5.8 6.8 ns t plh leab b 1.5 8.7 9.7 1.5 8.2 9.2 ns t phl leab b 1.5 6.5 6.9 1.5 6.2 6.7 ns t plh leba a 1.5 7.8 9.2 1.5 7.4 8.4 ns t phl leba a 1.5 6 6.6 1.5 5.7 6.4 ns t pzh oeab or oeba bora 1.5 8.4 9.6 1.5 7.9 8.7 ns t pzl oeab or oeba b or a 1.5 8.4 9.6 1.5 7.9 8.7 ns t phz oeab or oeba bora 2.5 9.1 9.3 2.5 8.4 8.9 ns t plz oeab or oeba b or a 2.5 9.1 9.3 2.5 8.4 8.9 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see figure 14) sn54lvth182512 sn74lvth182512 parameter from (input) to (output) v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max f max tck 50 40 50 40 mhz t plh tck ???? ?? ? ? ?? ? ?? ?? ? ?? ??k ? ?? ? ?? ? ? ?? ? ?? ?? ? ?? ??k ?? ? M ? ? ? M? ?? ? ?? ??k ?? ?? ? ?? M? ?? ?? ? ?? ??k ???? ? ?? ?? ? ?? ? ?? ??k ? ?? ? ? ?? ?? ? ?? ? ?? ??k ?? ? M ? ? ? M? ?? ? ?? ??k ?? ?? M ? ?? ? M? ?? ? ?? ??k ???? ? ?? ? ? ?? ? ?? ??k ? ?? ? ? ??? ?? ??? ?? ? ?? ??k ?? ?? ?? ?? ? ?? ?? ? ?? ??k ?? ?? ?? ?? ?? ? ?? product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lvth18512, sn54lvth182512, sn74lvth18512, sn74lvth182512 3.3-v abt scan test devices with 18-bit universal bus transceivers scbs671b august 1996 revised october 1997 33 post office box 655303 ? dallas, texas 75265 parameter measurement information 1.5 v t h t su from output under test c l = 50 pf (see note a) load circuit s1 6 v open gnd 500 w 500 w data input timing input 1.5 v 2.7 v 0 v 1.5 v 1.5 v 2.7 v 0 v 2.7 v 0 v 1.5 v 1.5 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 2.7 v 0 v 1.5 v 1.5 v input 1.5 v output control output waveform 1 s1 at 6 v (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh 0.3 v 0 v 2.7 v voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 6 v gnd test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. figure 14. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 74lvth182512dggre4 active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74lvth18512dggre4 active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth182512dggr active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth18512dggr active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 5-sep-2005 addendum-page 1
mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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